1. Field of the Invention
The present invention relates to a demodulation circuit for demodulating a reception signal.
2. Description of the Related Background Art
As a conventional demodulation circuit of this type, for example, a light reception circuit disclosed in IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-28, NO. 2, FEBRUARY, 1981 is known, and is shown in FIG. 1.
The drain of a field effect transistor (FET) Q1 is connected to an FET Q2 of which function is a load of the FET Q1, and its source is grounded. An FET Q3, diodes D1 to D4, and an FET Q4 constitute a source-follower circuit, and are formed so that an output impedance of the circuit is 50 .OMEGA.. A positive power supply voltage V.sub.DD of +5 V is applied to the drains of the FETs Q2 and Q3, and a negative power supply voltage V.sub.SS of -4 V is applied to the source of the FET Q4.
A received light signal is converted into an electrical signal, and the electrical signal is supplied to the FET Q1 as a gate voltage V.sub.gs to be converted to a drain current I.sub.d. The drain current I.sub.d flows to have the FET Q2 as a load, and a voltage is generated at the drain of the FET Q1. Since this voltage is applied to the gate of the FET Q3, the FET Q3 is turned on, and a drain current I.sub.d also flows through the diodes D1 to D4, and a predetermined voltage is generated at the drain of the FET Q4. Thus, this predetermined voltage is output.
In the conventional circuit shown in FIG. 1, however, when a strong light signal is received, the amplitude of a signal input to the circuit is increased. For this reason, distortion of a signal to be demodulated is increased, and linearity of a demodulated signal is impaired. This poses a serious problem in a system which is required to demodulate an analog signal as a reception signal with excellent linearity.
A cause of impairing linearity is as follows. That is, in gate voltage V.sub.gs vs. drain current I.sub.d characteristics as I/O characteristics of an FET, the drain current I.sub.d is expressed as a quadratic function of the gate voltage V.sub.gs, and is given by the following equation: EQU I.sub.d =K(V.sub.gs -V.sub.th).sup.2 ( 1)
where V.sub.th is the threshold voltage of the FET, and K is the proportional constant serving as a reference for a current driving capacity.
Therefore, when the reception signal applied to the FET as the gate voltage V.sub.gs is increased, the drain current I.sub.d is nonlinearly changed, and linearity of a demodulated signal is impaired.
A light reception circuit shown in FIG. 2 is also known.
A voltage V.sub.B is applied to a light-receiving element 1. A light signal received by the light-receiving element 1 is converted to a voltage signal by a resistor R1. A DC component of this voltage signal is removed by a capacitor C1, and the voltage signal is applied to the gate of an FET Q5. A predetermined voltage is applied to the gate of the FET Q5 by resistors R2 and R3. The voltage signal from which the DC component is removed is impedance-converted by a source-follower circuit constituted by the FET Q5 and a resistor R4. The impedance-converted voltage signal is output from the source of the FET Q5.
In the conventional circuit shown in FIG. 2, when the resistors R2 and R3 are appropriately selected, the gate voltage of the FET Q5 can be desirably selected. However, the gate voltage fluctuates due to manufacturing variations of, e.g., a threshold voltage, a transfer conductance g.sub.m, and the like of the FET Q5, and a fluctuation in power supply voltage V.sub.DD. Therefore, a demodulated signal cannot be stabilized, and linearity is impaired.